Synopsys (SNPS)

Chip-design software (EDA) + silicon IP — the tools used to design semiconductors

AI exposure 30% — derived from reported segment revenue, not asserted.

Where it sits

Software Stack → EDA & Engineering Software · figures rebased to Q3 FY2026, reported 2026-08-26

Chip-design software. The EDA & Engineering Software sub-tier is defined as the tools every semiconductor is designed with — a tight duopoly, which after this correction is exactly what it contains: Synopsys and Cadence.

Reported segments

• Design Automation — 80.9% of revenue
• Design IP — 19.1% of revenue

Synopsys ($2,476.8M Q3 FY2026, +42.4% YoY). Design Automation 80.9% ($2,003.0M, +52.7%, 45.2% adjusted operating margin) and Design IP 19.1% ($473.8M, +10.8%, 26.5% margin). The mix moved 5.5 points toward Design Automation in a year, which is the Ansys acquisition landing inside the segment rather than the IP business shrinking — Design IP still grew, just at a fifth of the rate. The EDA-versus-Ansys split within Design Automation is not disclosed and is held at the prior Atlas ratio.

How the 30% is built

• Design Automation — 80.9% of revenue × 28% AI-driven (disclosed). EDA and Ansys simulation are sold across every end market — automotive, industrial, aerospace, consumer — with AI silicon design the fastest-growing slice but still a minority of seats
• Design IP — 19.1% of revenue × 40% AI-driven (disclosed). Interface IP (HBM, PCIe, UCIe, Ethernet) is disproportionately bought for AI accelerators and the memory around them, so it carries a higher AI share than the design-tool business

Investment read

Moat. EDA duopoly with Cadence, now extended from silicon into systems simulation by the completed Ansys acquisition — design flows are foundry-certified and multi-year, so switching means requalifying the flow rather than swapping a tool. 84% of revenue is recurring against an $11.0B RPO, roughly 1.1x forward annual revenue.

Bottleneck / pricing power. Strong pricing power in core EDA (mission-critical, embedded, subscription) — FY2026 non-GAAP operating margin guided to ~41%. The soft leg is Design IP, where revenue fell ~6% YoY to $454M in Q2 FY2026 and segment margin compressed from 31% to 24% as the model re-orients toward hyperscaler custom engagements.

Role in the AI stack. The chip-design-tool (EDA) layer — every AI chip is designed here.

Connected companies

• NVIDIA (NVDA) — SNPS supplies: EDA tools + IP
• Broadcom (AVGO) — SNPS supplies: EDA + design IP
• Cadence Design Systems (CDNS) — SNPS competes with: EDA duopoly — SNPS + CDNS + Siemens EDA ~75% of market; SNPS post-Ansys broadest
• Dassault Systèmes (DSY) — SNPS competes with: Overlap is multiphysics simulation — Dassault SIMULIA/Abaqus vs Synopsys-owned Ansys — not core EDA
• Arm Holdings (ARM) — SNPS supplies: EDA tools + IP co-optimization for Arm cores (Arm Total Design partner, 3-decade collaboration, Neoverse CSS)
• Lattice Semiconductor (LSCC) — SNPS supplies: EDA tools for Lattice FPGA design
• Advanced Micro Devices (AMD) — SNPS supplies: EDA tools + IP for AMD chip design
• Qualcomm (QCOM) — SNPS supplies: EDA tools + IP for QCOM chip design
• Marvell Technology (MRVL) — SNPS supplies: EDA tools + IP for MRVL chip design
• NXP Semiconductors (NXPI) — SNPS supplies: EDA tools + IP for NXPI chip design
• ON Semiconductor (ON) — SNPS supplies: EDA tools + IP for ON chip design
• Microchip Technology (MCHP) — SNPS supplies: EDA tools + IP for MCHP chip design
• STMicroelectronics (STM) — SNPS supplies: EDA tools + IP for STM chip design
• Texas Instruments (TXN) — SNPS supplies: EDA tools + IP for TXN chip design

Others in EDA & Engineering Software

• Cadence Design Systems (CDNS)
• Autodesk (ADSK)
• Dassault Systèmes (DSY)
• Bentley Systems (BSY)

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