Cadence Design Systems (CDNS)

Chip-design software (EDA) + IP + multiphysics simulation — co-leader with Synopsys

AI exposure 30% — derived from reported segment revenue, not asserted.

Where it sits

Software Stack → EDA & Engineering Software · figures rebased to Q2 2026, reported 2026-07-27

Chip-design software. The EDA & Engineering Software sub-tier is defined as the tools every semiconductor is designed with — a tight duopoly, which after this correction is exactly what it contains: Synopsys and Cadence.

Reported segments

Core EDA — 68% of revenue
IP — 13.8% of revenue
System Design & Analysis (SDA) — 18.2% of revenue

Cadence ($1.584B Q2 2026, +24% YoY; recurring revenue 78% of the total). Core EDA 68% (+18%) = primary B5 EDA & Engineering Software — digital, custom and analog design plus a record quarter in emulation hardware on AI and HPC demand; IP 13.8% (+40%, driven by AI and HPC needs for data movement and memory bandwidth — HBM4, 224G SerDes); System Design & Analysis 18.2% (+37%, including the Hexagon Design acquisition). Cadence disclosed Core EDA as a share and the other two only as growth rates, so the 13.8/18.2 split is an Atlas estimate at the prior ratio.

How the 30% is built

Core EDA — 68% of revenue × 30% AI-driven (disclosed). Every chip including AI silicon is designed on it; the emulation hardware inside is explicitly AI and HPC driven
IP — 13.8% of revenue × 35% AI-driven (estimate). HBM4 and 224G SerDes interface IP is specified disproportionately into AI accelerators and networking silicon
System Design & Analysis (SDA) — 18.2% of revenue × 25% AI-driven (estimate). Multiphysics simulation serves mechanical and electronic system design broadly, with data-centre thermal and power a growing slice

Investment read

Moat. EDA duopoly (with Synopsys) + design IP + system-design expansion; the other half of the indispensable chip-design-tool duopoly.

Bottleneck / pricing power. Strong pricing power — duopoly, embedded in foundry-certified design flows, mission-critical, ~80% recurring, with a record $8.1B backlog and billings +31% YoY outrunning a 24%-growth quarter. The constraint is policy rather than competition: China is ~12-13% of revenue and the raised FY2026 guide explicitly assumes export regulations remain substantially unchanged.

Role in the AI stack. The chip + system design-tool (EDA) layer.

Connected companies

NVIDIA (NVDA) — CDNS supplies: EDA verification
Advanced Micro Devices (AMD) — CDNS supplies: EDA tools
Synopsys (SNPS) — CDNS competes with: EDA duopoly — SNPS + CDNS + Siemens EDA ~75% of market; SNPS post-Ansys broadest
Broadcom (AVGO) — CDNS supplies: EDA tools + IP for Broadcom advanced-node ASIC design (AI-driven design flow collaboration)
Arm Holdings (ARM) — CDNS supplies: EDA tools + design flow for Arm IP implementation/verification
Qualcomm (QCOM) — CDNS supplies: EDA tools + IP for QCOM chip design
Marvell Technology (MRVL) — CDNS supplies: EDA tools + IP for MRVL chip design
NXP Semiconductors (NXPI) — CDNS supplies: EDA tools + IP for NXPI chip design
ON Semiconductor (ON) — CDNS supplies: EDA tools + IP for ON chip design
Microchip Technology (MCHP) — CDNS supplies: EDA tools + IP for MCHP chip design
STMicroelectronics (STM) — CDNS supplies: EDA tools + IP for STM chip design
Texas Instruments (TXN) — CDNS supplies: EDA tools + IP for TXN chip design
Analog Devices (ADI) — CDNS supplies: EDA tools + IP for ADI chip design
GlobalFoundries (GFS) — CDNS supplies: EDA tools + IP for GFS chip design

Others in EDA & Engineering Software

All 174 companies · What moved this quarter · How the map is built