Memory-interface chips + IP — buffer/RCD chips that enable high-speed DRAM/HBM
AI exposure 41% — derived from reported segment revenue, not asserted.
Silicon Layer → Memory & Storage ICs · figures rebased to Q2 2026, reported 2026-07-27
Memory interface chips (DDR5 RCD, buffers, PMICs for server DRAM/HBM) leads 3 businesses in this sub-tier that together are 100% of revenue, so Memory & Storage ICs is effectively the whole company rather than one leg of it.
Rambus ($207.4M Q2 2026, a record). Product 47.8% ($99.2M — DDR5 register clock drivers, buffers and PMICs for server DIMMs) = primary B1 Memory & Storage ICs; Royalty & Licensing 40.6% ($84.2M, royalties +22% YoY on AI-driven memory demand); Contract & Other 11.6% ($24.0M). The product share fell from 60% to 47.8% not because chips weakened but because royalties grew faster — Rambus monetises the same memory cycle twice, through silicon and through patents.
Moat. Memory-interface IP plus DDR5 RCD and buffer silicon — a small, design-locked toll on server DRAM at roughly mid-40% RCD share, where displacement means a 12-18 month module requalification. HBM4E interface IP added a next-generation design win at a Tier-1 US hyperscaler, extending the royalty book two to three years forward on top of 100+ prior HBM design wins.
Bottleneck / pricing power. Real pricing power in the interface niche plus a near-100%-margin licensing annuity — royalties reached $84.2M in Q2 2026 against $68.6M a year earlier. The mix is diluting it: product revenue carries a 60-65% long-term gross-margin target and is growing at roughly twice the pace of licensing, and TTM net margin has already slipped to 31.7% from 35.5%.
Role in the AI stack. The memory-interface layer — enables high-speed DRAM/HBM links.
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